ENES-244 Digital Logic Design

This course will introduce the basic principles and design procedures of digital systems at the gate and intermediate chip levels for electrical engineering students. The student will acquire knowledge of gates, flip-flops, registers, counters, Karnaugh maps, PAL devices, and synchronous sequential circuit design and analysis.

Credits

3

Prerequisite

ENES-100 and MATH-153

Hours Weekly

4 hours lecture weekly

Course Objectives

1. 1. Convert between decimal, binary, octal, and hexadecimal number systems.
2. 2. Perform two-level logic minimization using Boolean algebra, Karnaugh maps, and the
   Quine-McCluskey tabular minimization method.
3. 3. Describe the many types of logic gates.
   
4. 4. Perform binary addition and subtraction.
5. 5. Incorporate medium scale integrated circuits, like decoders, encoders, multiplexers, etc., into circuit
   design.
6. 6. Design and analyze clocked sequential circuits.
7. 7. Use various types of latches and flip-flops to build binary memory.
8. 8. Trace signals through various registers and counters.
9. 9. Describe various types of memory parity and error correction algorithms.
   
10. 10. Program PLA, PAL, SPLD devices.
11. 11. Use algorithmic state machine notation.
12. 12. Perform asynchronous sequential logic analysis.

Course Objectives

1. 1. Convert between decimal, binary, octal, and hexadecimal number systems.
2. 2. Perform two-level logic minimization using Boolean algebra, Karnaugh maps, and the
   Quine-McCluskey tabular minimization method.
3. 3. Describe the many types of logic gates.
   
4. 4. Perform binary addition and subtraction.
5. 5. Incorporate medium scale integrated circuits, like decoders, encoders, multiplexers, etc., into circuit
   design.
6. 6. Design and analyze clocked sequential circuits.
7. 7. Use various types of latches and flip-flops to build binary memory.
8. 8. Trace signals through various registers and counters.
9. 9. Describe various types of memory parity and error correction algorithms.
   
10. 10. Program PLA, PAL, SPLD devices.
11. 11. Use algorithmic state machine notation.
12. 12. Perform asynchronous sequential logic analysis.